The present invention relates to CMOS integrated circuit device structures and fabrication methods, and more particularly to transistor doping profiles in self-aligned gate processes.
FIG. 1 shows a portion of a prior-art CMOS integrated circuit device formed on a substrate 10 and including representative p-channel and n-channel transistors 1, 3. The p-channel transistor 1 has a gate electrode 2 and the n-channel transistor 3 has a gate electrode 4, both electrodes formed over a gate oxide 24 and both separated by isolation dielectric 16. The gate oxide 24 and the isolation dielectric 16 overlie n-type 12 and p-type 14 silicon regions of the silicon substrate 10. Using conventional fabrication techniques, the n-type silicon region 12 is masked off and an n+ type dopant is implanted in the p-type silicon region 14 not covered by the gate electrode 4 or isolation oxide 16 to form the source and drain regions 6 of the n-channel transistor 3. Then, the n-type silicon region 12 is unmasked and the p-type silicon region 14 is masked. P+ type dopant is then implanted in the n-type silicon region 12 not covered by the gate electrode 2 or isolation oxide 16 to form the source and drain regions 5 of the p-channel transistors 1. The mask is then removed and the device formation is completed typically by depositing a dielectric over the transistors and forming connections to the source, drain, and gate of each of the transistors using conventional metallization layers.
As device size, and particularly channel length, is reduced, conventional drain structure MOS devices can become unreliable due to short channel effects, such as hot carrier effects. Conventional drain structure n-channel MOS devices 3 can become unreliable at longer channel lengths due to short channel effects than conventional drain structure p-channel MOS devices 1.
One way to overcome this problem is to modify the conventional drain structure such that the peak electric field at the drain edge is reduced. This can be done by reducing the drain doping density at the drain edge to produce a lightly doped drain (LDD) structure in the device. The LDD structure in the device may be formed by employing a sidewall spacer of silicon dioxide on the gate material.
FIG. 2 shows complementary n-channel 19 and p-channel 17 MOSFETs with LDDs 8, 11, which are typical of a plurality of such MOSFETs in a CMOS IC device. In a conventional process for forming LDD MOSFETs using CMOS technology, n-type 12 and p-type 14 wells are defined in a silicon substrate 10 and are isolated by isolation oxide 16. The gate oxide 24 is then formed and polysilicon gate electrodes 20, 22 are patterned on the gate oxide 24. The p-type silicon region 14 is then masked off and p-type dopant is then implanted into the n-type silicon region 12 to form the LDD regions 8 of the p-channel source and drain regions 7. The p-type silicon region 14 is unmasked and the n-type silicon region 12 is then masked off. N-type dopant is implanted into the p-type silicon region 14 to form the LDD regions 11 of the n-channel source and drain regions 9. The mask is then removed. A layer of silicon dioxide 2000-5000 xc3x85 thick is deposited over the device and then the silicon dioxide is anisotropically etched back to form oxide sidewall spacers 13, 15 on the gate electrodes 20, 22. The p-type silicon region 14 is again masked off and p+ dopant is implanted into the n-type silicon region 12 to form the p-channel source and drain regions 9. The mask is then removed. The n-type silicon region 14 is masked off and n+ dopant is implanted to form the n-channel source and drain regions 9. The device processing is completed using conventional techniques to form conductive interconnect and insulating layers.
A problem in employing the known sidewall spacer technology in the manufacture of an LDD device is that the p-channel devices must be masked during the LDD processing of the n-channel devices, and the n-channel devices must be masked during the LDD processing of the p-channel devices, since the LDD implant penetrates all unmasked areas of the CMOS device being fabricated. Accordingly, an extra masking layer is required to protect areas of the n-channel devices during the manufacture of the p-channel devices and another extra masking layer is required to protect areas of the p-channel devices during the manufacture of the n-channel devices.
FIGS. 3 shows two of a plurality of complementary n-channel 23, and p-channel 21, MOSFETS with LDDs 8, 11 manufactured according to a conventional method of manufacturing LDD devices using removable sidewall spacers. The n-type and p-type wells 12, 14 are defined in the silicon substrate 10 and are isolated by isolation oxide 16. Gate oxide 24 is then formed and polysilicon gate electrodes 20, 22 are patterned on the gate oxide 24. A layer of oxide or nitride is deposited over the device and is then anisotropically etched back to form sidewall spacers adjacent to the gate electrodes 20, 22. The p-type silicon region 14 is masked off and p+ dopant is implanted into the n-type silicon region 12 to form the p-channel source and drain regions 7. The mask is removed and the n-type silicon area 12 is masked off. N+ dopant is implanted to form the n-channel source and drain regions 9. The mask is removed and then the sidewall spacers are removed. The p-type silicon region 14 is then masked off and p-type dopant is implanted into the n-type silicon region to form the LDD regions 8 of the p-channel source and drain regions 7. The p-type silicon region 14 is unmasked and then the n-type silicon region 12 is masked off. N-type dopant is implanted into the p-type silicon region 14 to form the LDD regions 11 of the n-channel source and drain regions 9. The mask is then removed. The device processing is completed using conventional techniques to form conductive interconnect and insulating layers.
One problem with using the removable sidewall spacer technology in the manufacture of an LDD device is that again the p-channel device must be masked during the LDD processing of the n-channel device, and the n-channel device must be masked during the LDD processing of the p-channel device. Another problem is that the sidewall spacers must be removed by an etch process before the LDD implants. Accordingly, in addition to the two extra masking layers required during the manufacture, one in the manufacture of the p-channel devices, and one in the manufacture of the n-channel devices, an extra etch is also required in the manufacture of the device.
Alternatively, the removable sidewall spacer technology can be used with only two masking steps, as described in Campbell et al., xe2x80x9cMOSFET and Fabrication Method,xe2x80x9d U.S. Pat. No. 5,087,582, assigned to Inmos Ltd. Still referring to FIG. 3, after the p+ dopant is implanted into the n-type silicon region 12 to form the p-channel source and drain regions 7, while the p-type silicon region 14 is masked off, the sidewall spacers above the n-type silicon region 12 are removed and p-type dopant is then implanted into the n-type silicon region 12 to form the LDD regions 8 of the p-channel source and drain regions 7. The mask is removed and then the n-type silicon area 12 is masked off. N+ dopant is implanted to form the n-channel source and drain regions 9. The sidewall spacers above the p-type silicon region 14 are removed. N-type dopant is implanted in to the p-type silicon region 14 to form the LDD 11 regions of the n-channel source and drain regions 9. The mask is then removed. The device processing is completed using conventional techniques to form conductive interconnect and insulating layers.
A problem with using this alternative removable sidewall spacer technology in the manufacture of an LDD device is that the sidewall spacers must be removed from the p-type silicon region by an etch process before forming the LDD implants in the n-channel transistor, and the sidewall spacers must be removed by a separate etch from the n-type silicon regions before forming the LDD implants in the p-channel transistor. Accordingly, an extra etch is required during the manufacture of the p-channel devices and another extra etch is required during the manufacture of the n-channel devices.
A method of fabricating an integrated circuit having n-channel and p-channel transistors in a CMOS device is provided in accordance with the present invention. The method includes forming gate electrodes over n-type and p-type silicon regions that define isolated active areas of the device, implanting an n-type dopant into the p-type silicon to form LDD regions of the n-channel transistor. A first insulating layer is then formed over the gate electrodes and the n-type silicon regions are then implanted with a p+ type dopant impurity to form the low to resistivity source and drain regions of the p-channel transistor. A second insulating layer is formed over the first insulating layer. The first and second insulating layers are then etched to provide the sidewall spacers. The p-type silicon regions are then implanted with an n+ type dopant impurity to form the low resistivity regions of the n-channel transistor.
The resulting CMOS integrated circuit has a plurality p-channel transistors formed in active surface areas of n-type regions and a plurality of n-channel transistors formed in isolated active surface areas of p-type regions. Each of the p-channel and n-channel transistors has a gate electrode which overlies and is insulated from the respective active surface. The integrated circuit further contains p-channel source and drain regions each consisting of a low resistivity region, and n-channel source and drain regions, each having a low resistivity region and an LDD region. Each gate electrode having a pair of sidewall spacers having an inner and an outer portion each corresponding to an underlying source and drain region. Each p-channel low resistivity region is located under the outer portion and at least a part of the inner portion of its respective sidewall spacer. Each n-channel low resistivity region is located under at least a part of the outer portion and a part of the inner portion of its respective sidewall spacer. Each n-channel LDD region extends from its respective low resistivity region to underlie the inner portion of its respective sidewall spacer.